The subject invention relates to data modem circuitry and more particularly to a gain control circuit for detecting and correcting a false equilibrium condition generated in adaptively equalized modems.
Many adaptively equalized data modems employing vestigial sideband (VSB) or quadrature amplitude (QAM) modulation techniques utilize slicing or decision circuits to assign the equalizer output to one of a plurality of possible ideal data levels.
Present art teaches that the "slicer" or decision circuit for modem receivers should produce as an output the ideal point that is closest to the slicer input. (This minimizes the number of errors in the presence of additive white noise at the input to the receiver.) When this slicer rule is followed on a multilevel, automatically equalized system, false equilibrium can arise whereby the equalizer tap settings are correct except for a scale factor and possibly a rotation, (the scale factor and rotation being constant for each and every equalizer tap.)
In any event, this false equilibrium phenomena is characterized by the fact that the equalizer has successfully resolved the transmitted signal into distinct regions, but because the overall system gain is incorrect, the slicer does not assign the received signal to the correct ideal point.
Modems are subject to a phenomenon known as amplitude hits whereby the gain of the transmission medium changes suddenly, then remains at the new gain for a relatively long period. Amplitude hits of a sufficiently large decrease in magnitude may in fact cause the system to seek a false equilibrium.